The present invention relates in general to communication between multiple data processors and, more particularly, to communication between multiprocessors using a switch protocol.
Communication between computers has become an important aspect of everyday life in both private and business environments. Computers converse with each other based upon a physical medium for transmitting the messages back and forth, and upon a set of rules implemented by electronic hardware attached to and programs running on the computers. These rules, often called protocols, define the orderly transmission and receipt of messages in a network of connected computers.
The use of multiple processors in a single system is well-known in the field of data processing systems, and the resulting systems are called multiprocessor systems. As data processing systems have expanded to incorporate multiprocessors, communication systems for allowing communication between the multiple processors have been proposed. The multiprocessor communication systems must be continually improved to allow for greater data processing capacity and faster speeds the multiprocessor environment is capable of delivering.
To improve upon the presently known multiprocessor communication systems, the present invention has been proposed. The present invention provides a system for inter-processor communication in a backplane based multiprocessor system. According to one aspect of the invention, provided is a communication system that implements the Ethernet MAC protocol over a backplane physical media that can take advantage of the Ethernet MAC that is built into many processors. According to another aspect of the present invention, provided is a protected communication system that provides redundancy at all levels within the system.
The present invention provides many advantages over the presently known communication systems for multiprocessors. Not all of these advantages are simultaneously required to practice the invention as claimed, and the following list is merely illustrative of the types of benefits that may be provided, alone or in combination, by the present invention. These advantages include: (1) the use of a standard Ethernet protocol to take advantage of the design simplification but without the cost, space, and power that normal Ethernet physical media requires; (2) providing a redundant communication system wherein each processor has a redundant communication path and wherein the redundancy is transparent to the processors; (3) communicating over a low power low voltage differential signal (LVDS) channel without the need for signal shaping, the use of an analog phase locked loop (PLL), or magnetic components typical of Ethernet systems; (4) providing a soft reset mechanism; (5) providing a mechanism for monitoring the link status of both connections, simultaneously; and (6) providing each processor with a full 10 Mbs connectivity to a non-blocking Ethernet switch.
In accordance with one aspect of the present invention, a multiprocessor system is provided that has a plurality of processor modules coupled together via a backplane. The system comprises a first processor module having a first processor and a switch with a plurality of I/O ports and a plurality of communication paths coupled to the I/O ports of the switch, the switch being operable to route data packets formatted according to an Ethernet MAC protocol. The system further comprises a second processor module having a second processor and a first communication device that is operable to communicate with the switch via a first communication path on the backplane. The system also comprises a third processor module having a third processor and a second communication device that is operable to communicate with the switch via a second communication path on the backplane. The switch is operable to route Ethernet MAC protocol data packets from one of the first, second or third processors to another of said first, second or third processors.
In accordance with another aspect of the present invention a multiprocessor system is provided that has a plurality of processor modules coupled together via a backplane. The system comprises a first processor module having a first processor and a first switch with a plurality of I/O ports and a plurality of communication paths coupled to the I/O ports of the first switch, the first switch being operable to route data packets. The system further comprises a second processor module having a second processor and a second switch with a plurality of I/O ports and a plurality of communication paths coupled to the I/O ports of the second switch, the second switch being operable to route data packets. The system also comprises a third processor module having a third processor and a first communication device that is operable to communicate with the first switch via a first communication path on the backplane and operable to communicate with the second switch via a second communication path on the backplane. In addition, the system comprises a fourth processor module having a fourth processor and a second communication device that is operable to communicate with the first switch via a third communication path on the backplane and operable to communicate with the second switch via a fourth communication path on the backplane. The first switch is operable to route data packets from one of the first, second, third or fourth processors to another of the first, second, third or fourth processors. The second switch is also operable to route data packets from one of the first, second, third or fourth processors to another of the first, second, third or fourth processors.